1. Technical Field
The present invention relates to a configuration for protection from over-current in a digital amplifier driving a load.
2. Related Art
In a power amplifier driving a load connected to an output terminal, if an incorrect connection (user caused incorrect wiring, short-circuit, and so forth) occurs, such as between the output terminal and a power supply or between power supply terminals, an over-current flows to an output transistor for outputting a driving signal to the load connected to the output terminal so that failure of the output transistor easily occurs. Therefore, an over-current protective measure has been provided in the related art to protect the output transistor by detecting over-current flowing to the output transistor.
FIG. 1 shows a block diagram of an output section of a digital amplifier provided with an over-current protective measure of the related art. The digital amplifier has an amplifier output section at an output terminal OUT to which a load L is connected. The amplifier output section has a high-voltage (source) output transistor Q1 provided between a high-voltage power supply PVD and the output terminal OUT and a low-voltage (sink) output transistor Q2 provided between a low-voltage power supply (ground GND) and the output terminal OUT.
To a gate of the high-voltage output transistor Q1 is connected a high-voltage amplifier driver 80H and to a gate of the low-voltage output transistor Q2 is connected a low-voltage amplifier driver 80L.
In accordance with pulse signals corresponding to PWM (Pulse Width Modulation) signals supplied from a PWM signal generator that is not shown, the amplifier drivers 80H and 80L drive the corresponding high-voltage output transistor Q1 and the low-voltage output transistor Q2 on and off. The high-voltage output transistor Q1 and the low-voltage output transistor Q2 do not turn on simultaneously. When the high-voltage output transistor Q1 turns off and the low-voltage output transistor Q2 turns on, a load driving signal at GND level (0 V) is output from the output terminal OUT. On the other hand, when the low-voltage output transistor Q2 turns off and the high-voltage output transistor Q1 turns on, a voltage corresponding to the high-voltage power supply PVD (8 V to 26 V) is applied to the output terminal OUT via the high-voltage output transistor Q1.
The digital amplifier of FIG. 1 employs N-channel FETs for both the above-mentioned output transistors Q1 and Q2. Furthermore, a bootstrap method is employed, and a common power supply Vcc of 5 V, for example, is employed as the high-voltage power supply for both the above-mentioned amplifier drivers 80H and 80L for driving the output transistors Q1 and Q2 so that the amplifier drivers 80H and 80L operate under equal voltage conditions and driving signals having equal voltages are also supplied to the output transistors Q1 and Q2 so as to control these transistors. A boot capacitor C1 is connected between the output terminal OUT and a boot terminal Boot. The boot capacitor C1 is charged by the above-mentioned common power supply, which is connected to the boot terminal Boot. When the high-voltage output transistor Q1 turns on, the output voltage at the output terminal OUT rises in accordance with the holding voltage of the boot capacitor C1, and in the on-state period of the above-mentioned high-voltage output transistor Q1, the “high-voltage power supply PVD (26 V)+holding voltage (≠5 V) of capacitor C1”, namely, a load driving signal of 31 V in this example is output from the output terminal OUT.
In the digital amplifier of the bootstrap method described above, a high-voltage detection line 98H is connected to the high-voltage power supply PVD for the high-voltage output transistor Q1 and a sensing signal obtained from the high-voltage detection line 98H is supplied to a high-voltage over-current detector 90H. Furthermore, a low-voltage detection line 98L is connected to the output terminal OUT of the low-voltage output transistor Q2 and a sensing signal obtained from the low-voltage detection line 98L is supplied to a low-voltage over-current detector 90L.
The power supply PVD voltage for the output transistor Q1 is always supplied to the high-voltage over-current detector 90H and the output terminal OUT voltage for the output transistor Q2 is always supplied to the low-voltage over-current detector 90L.
For example, when the output terminal OUT is shorted to GND, an over-current flows to the high-voltage output transistor Q1 so that the existence of an on-state resistance of the output transistor Q1 causes the voltage of the sensing signal obtained via the high-voltage detection line 98H to rise above the normal value. When the high-voltage power supply PVD is shorted to the output terminal OUT, an over-current flows to the low-voltage output transistor Q2 so that the existence of an on-state resistance of the output transistor Q2 causes the voltage of the sensing signal obtained via the low-voltage detection line 98L to rise above the normal value. Even when the PVD is shorted to GND, the residual voltages of the output transistors Q1 and Q2 rise in the same manner above the normal voltages.
Therefore, when an over-current is generated at the output transistors Q1 and Q2 due to a short-circuit or other cause, the high-voltage over-current detector 90H and the low-voltage over-current detector 90L can detect the generation of over-current on the basis of the corresponding sensing signal.
When the generation of an over-current is detected in the over-current detectors 90H and 90L described above, the over-current detectors 90H and 90L generate an over-current detecting signal, and in accordance with this over-current detecting signal, the high-voltage and low-voltage amplifiers 80H and 80L stop operating and the output transistors Q1 and Q2 stop operating. Therefore, the power amplifier can be protected from over-current.
However, to the high-voltage detection line 98H and the low-voltage detection line 98L is always input a sensing signal having large amplitude (between the power supply voltage and the output terminal voltage) in accordance with the amplitude of the load driving signal from the output terminal OUT. The sensing interval is the voltage between PVD and OUT for the high-voltage over-current detector 90H and the voltage between OUT and GND for the low-voltage over-current detector 90L. Thus, with regard to the high-voltage detection line 98H, the supplied sensing signal is the voltage between the power supply PVD and OUT and the reference voltage of the high-voltage detection line 98H is OUT. Now, if there is a low resistance short to GND when the output transistor Q1 is on, a current higher than normal flows so that a voltage drop corresponding to the on-state resistance of the output transistor Q1 is generated and the output voltage drops. As a result, the voltage across PVD and OUT increases and over-current is detected.
Therefore, in each of the sensing signal input section of the high-voltage over-current detector 90H and the low-voltage over-current detector 90L, it is necessary to use a circuit device capable of sufficiently withstanding sensing signals having large amplitudes. Furthermore, since sensing signals having large amplitudes are supplied to the high-voltage detection line 98H and the low-voltage detection line 98L, which are wired within the power amplifier, noise caused by sensing signals having large amplitudes is superimposed onto the peripheral circuitry, such as the amplifier drivers 80H and 80L, and PWM modulators (not shown), and there is the possibility of malfunction or noise generation.